VLSI System Design
VLSI System Design
Prof. A.N.Chandorkar,IITB
VLSI Digital Design flow & layout issues 1
VLSI Digital Design flow & layout issues 1
Prof. A.N.Chandorkar,IITB
VLSI Digital Design flow & layout issues 2
VLSI Digital Design flow & layout issues 2
Prof. A.N.Chandorkar,IITB
Digital Design : RTL Simulation
Digital Design : RTL Simulation
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : RTL Simulation
Digital Design : RTL Simulation
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : RTL Simulation
Digital Design : RTL Simulation
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : power pad insertion and formal verification
Digital Design : power pad insertion and formal verification
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : Physical Design - I/O ring and floorplan
Digital Design : Physical Design - I/O ring and floorplan
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : Physical Design - Power planning
Digital Design : Physical Design - Power planning
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : Physical Design - Place and route and GDSII
Digital Design : Physical Design - Place and route and GDSII
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : Inetgration - importing GDSII in virtuoso
Digital Design : Inetgration - importing GDSII in virtuoso
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design : Inetgration - Power cut and mixed signal integration
Digital Design : Inetgration - Power cut and mixed signal integration
Chandrashekhar Kukade,Research Scholar,VNIT
Digital Design: Hands on
Digital Design: Hands on
Chandrashekhar Kukade,Research Scholar,VNIT
Interconnect issues
Interconnect issues
Prof. D.K.Sharma,IITB
Interconnect drivers
Interconnect drivers
Prof. D.K.Sharma,IITB
Testing of interconnect driver performance
Testing of interconnect driver performance
Prof. D.K.Sharma,IITB
Testing of interconnect driver performance
Testing of interconnect driver performance
Prof. D.K.Sharma,IITB
Testing of interconnect driver performance
Testing of interconnect driver performance
Prof. D.K.Sharma,IITB
Analog Design: Schematic creation
Analog Design: Schematic creation
Anurag Zope,Research Scholar,VNIT
Analog Design: Symbol creation, simulation
Analog Design: Symbol creation, simulation
Anurag Zope,Research Scholar,VNIT
Analog Design: Layout creation, layout practices
Analog Design: Layout creation, layout practices
Anurag Zope,Research Scholar,VNIT
Analog Design: Layout creation, guard rings
Analog Design: Layout creation, guard rings
Anurag Zope,Research Scholar,VNIT
Analog Design: Layout verification, DRC, LVS, RCX, post layout simulation
Analog Design: Layout verification, DRC, LVS, RCX, post layout simulation
Anurag Zope,Research Scholar,VNIT
Analog Design: Integration for tape out, GDSII
Analog Design: Integration for tape out, GDSII
Anurag Zope,Research Scholar,VNIT
Analog Design: LEF generation, Layout issues and practices
Analog Design: LEF generation, Layout issues and practices
Anurag Zope,Research Scholar,VNIT
Analog Design: LEF generation, Layout issues and practices for RF
Analog Design: LEF generation, Layout issues and practices for RF
Anurag Zope,Research Scholar,VNIT
Fabrication issues
Fabrication issues
Prof. R.M.Patrikar,VNIT
Design for Manufacturability
Design for Manufacturability
Prof. R.M.Patrikar,VNIT
Lithography methods for CMOS fabrication, Temperature effects
Lithography methods for CMOS fabrication, Temperature effects
Prof. R.M.Patrikar,VNIT
Roughness modelling for simulation accuracy
Roughness modelling for simulation accuracy
Prof. R.M.Patrikar,VNIT
Layout to tape out
Layout to tape out
Marshnil Dave,Ph.D. Scholar,IITB
I/O pin sharing and DRC checks
I/O pin sharing and DRC checks
Marshnil Dave,Ph.D. Scholar,IITB
ERC checks and post-layout simulation speed up
ERC checks and post-layout simulation speed up
Marshnil Dave,Ph.D. Scholar,IITB
Pad frame and I/O pads
Pad frame and I/O pads
Marshnil Dave,Ph.D. Scholar,IITB
Matching and monte carlo simulation, tape out experience
Matching and monte carlo simulation, tape out experience
Marshnil Dave,Ph.D. Scholar,IITB

Hardware accelerated testing