Schematic Entry, Buiding the example Test design, Analog Simulation with Spectre
Schematic Entry, Buiding the example Test design, Analog Simulation with Spectre.
Mr. Kumaravel, Research Scholar NIT-T
Symbol Creation, Creating a layout view
Symbol Creation, Creating a layout view.
Mr. Kumaravel, Research Scholar NIT-T
Physical verification
Physical verification.
Mr. Kumaravel, Research Scholar NIT-T
Lab Session with Cadence Spectre and ADE
Lab Session with Cadence Spectre and ADE.
Mr. Kumaravel and Mr. Swaminathan, Research Scholar NIT-T
Lab Session with Cadence Spectre and ADE
Lab Session with Cadence Spectre and ADE.
Mr. Parthiban, M.Tech Student, NIT-T
Lab Session with Cadence Spectre and ADE
Lab Session with Cadence Spectre and ADE.
Mr. Parthiban, M.Tech Student, NIT-T
Layout Considerations for Analog Circuits
Layout Considerations for Analog Circuits.
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
Layout Considerations for Analog Circuits
Layout Considerations for Analog Circuits.
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
Layout Considerations for Analog Circuits
Layout Considerations for Analog Circuits
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
Layout Considerations for Analog Circuits
Layout Considerations for Analog Circuits
Dr. Laxminidhi, Assistant Professor NIT-Surathkal
RTL to GDS Flow
RTL to GDS Flow.
Mr. Prasanna Kumar, Research Scholar IIT Kanpur
RTL to GDS Flow
RTL to GDS Flow. Mr. Prasanna Kumar, Research Scholar IIT Kanpur
Digital Design Flow
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
Digital Design Flow
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
Digital Design Flow
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
Digital Design Flow
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
Digital Design Flow
Digital Design Flow.
Prof. Ramesh Kini, Professor NIT-Surathkal
RTL to GDS Flow (Back End Flow)
RTL to GDS Flow (Back End Flow).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
RTL to GDS Flow (Back End Flow)
RTL to GDS Flow (Back End Flow).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
Digital lab Session (Back End)
Digital lab Session (Back End).
Mrs. Shavitha Shenoy Mangalore & Mr. Prasanna Kumar
Integrating digital design with analog design
Integrating digital design with analog design.
Dr. Laxminidhi & Prof. Ramesh Kini
Sharing of IO pins, IO ring
Sharing of IO pins, IO ring.
Mr. Anurag (VNIT)
Sharing of Integration Experience
Sharing of Integration Experience.
Mr. Naveen/Diptiman (IBM Bangalore)
Steps in sending various files to IMEC, Measured results from previous tapeout
Steps in sending various files to IMEC, Measured results from previous tapeout.
Dr. Ramasamy, RMK EC
Working with memory compiler (FARADAY)
Working with memory compiler (FARADAY).
Mr. Mangesh, Mr. Sreenath (Intel)