SMDPII-VLSI:Special Manpower Development Programme in the area of VLSI Design,India

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Chip Integration and Tapeout Issues

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Home	>Instruction Enhancement Program SMDP II

Instruction Enhancement Programme

S.No	Name of the Institute	Date	Topic	No. of participants attended
1.	IIT Kanpur	July 3-14, 2006	Digital IC Design	21
2.	IIT Kharagpur	Sep 11-23, 2006	Low Power VLSI Design	24
3.	IIT Madras, Chennai	Nov 13-24, 2006	RF IC Design	27
4.	IISc Bangalore	Dec 4-15, 2006	Semiconductor Device Modeling & Simulation	18
5.	IIT Delhi	July 2-13, 2007	Analog IC Design	27
6.	IIT Kharagpur	Sep 24-Oct 05, 2007	VLSI-DSP based design	27
7.	IIT Kanpur	Dec 10-21, 2007	Synthesis of Digital System	25
8.	IISc Bangalore	Mar 10-19,2008	VLSI Testing & Verification	24
9.	IIT Kharagpur	May 12-17,2008	Technology CAD	11
10.	CEERI Pilani	Oct 14-18, 2008	Linux System Administration and EDA Tools Installation	26
11.	GEC,Goa (Conducted by IIT-Bombay )	March 16-21, 2009	Mixed-Signal VLSI Design	33
12.	IIT Delhi	July 13-18,2009	FPGA Laboratory	15
13.	Thapar University- Patiala (Organised by CEERI-Pilani)	December 14-23,2009	System Modeling Using System C/VHDL/Verilog	17
14.	IIT Madras	February 22-26,2010	Algorithms to Architectures	17
15.	IIT Kharagpur	March 2-13,2010	Low-Power,High Speed Digital Subsystem Design : Spec to Test	14
16.	NIT Trichy (Organised by IIT Madras)	Sept.29^th - Oct.2^nd,2010	Chip Integration and Tapeout Issues	27
17.	MNIT Jaipur (Organised by CEERI Pilani)	Dec.13^th - 17^th, 2010	Semiconductor Memory Design & Test	52
18.	IIT Kharagpur	March 6^th - 12^th , 2011	VLSI aspects on Biomedical Engineering	22
19.	IIT Delhi	March 14^th - 19^th, 2011	Low Power, Low Noise Operational Amplifier Design	20
20.	VNIT Nagpur (Organised by IIT Bombay)	Oct. 8^th - 10^th, 2011	Design Finishing for Chip Tape Out	25
21.	IIT Madras, IISc. Bangalore, IIT Delhi	Dec. 9^th - 12^th, 2011	Analog/Mixed Signal Design	50
22.	IIT Delhi	Jan. 16^th - 19^th, 2012	RFIC & System Design	20
23.	IIT Kanpur	Sept. 24^th - 28^th, 2012	Low Power Digital Design	24

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